Sue Fredette

Background

About Sue Fredette

Susan Fredette 10756 W. Prospector Dr Queen Creek AZ 85144 480 319 0538 (m) sueirvin1@hotmail.com EDUCATION M.A. Mathematics, Brigham Young University, Provo, Utah B.S. Mathematics-Statistics, Brigham Young University, Provo, Utah Teaching Credential, Brigham Young University, Provo Utah WORK EXPERIENCE: Innophase Corp. 9/24- present Intel Corp. 5/13 to 8/30/24 Fujitsu Corp. 2/13- 5/13 Broadcom. Irvine, CA 11/12 – 2/13 Analog and Mixed Signal Layout * Layout of large Analog, Mixed Signal blocks in 28nm process, Cadence OA tools Freescale Semiconductor, Tempe AZ 01/08 – 11/2012 Analog and Mixed Signal Layout Full Chip Layout, Floor planning, routing, laying out of block and leaf cells. Layout of Analog, Mixed Signal and Digital blocks. Layout of sensors and power management integrated circuits used in automotive and consumer products. ADC’s, DAC’s PLL circuits. In depth knowledge of analog layout and all it’s challenges. Cadence Virtuoso and Virtuoso XL, ASSURA, CALIBRE, Cadence 6.15 OA, Cadence 4.3, QRC parasitic extraction. TSMC 16/18 TSMC 55 Micron Corporation, Boise ID 07/01 – 12/07 Mask Designer. Unit Floor planning, layout of unit, leaf-cells and standard cells. Layout of Analog and Place and Route blocks. Cadence Virtuoso and Virtuoso XL, Hercules & Avanti verification. Pulsic Lyric Router. Intel Corporation 06/92 – 07/01 Mask Designer Fireball Execution Unit on Willamette MP Analog Pad and I/O structures, AD/DA circuits Data Cache Unit on the Deschutes MP Data Cache Unit on the P6 MP Responsibilities included: Top Level planning, placement and routing of large blocks of Circuitry Created synthesized blocks using APR tools, layout of data path blocks and sram arrays.