Suraj Mathew
Graphics Hardware Engineer at Intel
Based in Folsom, United States
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Seniority
Staff
Department
Engineering
Location
Folsom
Industry
Semiconductor Manufacturing
Company size
110K
Contact information
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s•••••••@intel.com
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Background
About Suraj Mathew
Around 15 years of ASIC/SoC pre-Si validation experience. • Experienced in architecture & development of IP level and SoC level Testbenches using SystemVerilog OVM/UVM methodologies. • Perfomed validation requirements gathering, tests content planning,content development, execution and issues debugs. • Experience in Gate level simulation and netlist debugs. • Into Python scripting • Experience in Graphics in Post-Silicon System validation role. • Have experience in managing an IP team in a Validation lead role. • Great team player and open clear communication.
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