Sushmitha Ramesh
Member of Technical Staff Physical Design Engineer(Sta) at Amd
Based in Ashburn, United States
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Seniority
Other
Department
Other
Location
Ashburn
Industry
Semiconductor Manufacturing
Company size
48K
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s•••••••@amd.com
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Background
About Sushmitha Ramesh
Passionate semiconductor professional with over 10 years of experience. Skilled in generating budget constraints, static timing analysis and timing closure for 6nm and below. Strong device physics knowledge with MS. in Microelectronics from National University of Singapore. Tools - Primetime, Synopsys IC compiler (ICC2), Synopsys Fusion Compiler Specialties - Budgeting, Static Timing Analysis, Constraints Development, RTL Integration, Timing Closure Programming - Cshell, Tcl, Perl Data Analysis - JMP, Excel
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