Sushmitha Shivashankar
Soc Design Engineer at Intel Corporation
Based in Sacramento, United States
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Seniority
Staff
Department
Engineering
Location
Sacramento
Industry
Semiconductor Manufacturing
Company size
110K
Contact information
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s•••••••@intel.com
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Background
About Sushmitha Shivashankar
Worked on SOC level RTL Integration and Verification as part of the SOC front-end design engineering team. Responsible for IP bring up, Integration into SOC, standard SOC flows check, and debugs for XEON processors. Hands on experience in developing the testbench components using System Verilog and responsible for executing, debug and resolved the issues seen in RTL and GLS netlist regression. Implementation of verification environments that include use of Constrained-random stimulus, System Verilog Assertions and coverage.
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