Tim Chen

Background

About Tim Chen

New Technology Developing(12-inch fab 10/5/2nm CMOS technology for Logic IC and SRAM) 1. Meet Customer’s requirement for competitive and stable baseline process 2. Co-work with Module for process knob finding by inline and physical check 3. Co-work with Defect team for baseline defect reduction and Product team for yield improvement by electrical and physical failure analysis 4. Co-work with Device team for performance confirming by split plan Dear Sirs, I am Tim Chen, I had been worked 8yrs at tsmc. There are 2 steps in my working experience. In first 6yrs, R&D for N10/N5 Technology node developing, it is first time to touch the fin FET MOS process. In N10. Responsible for FEOL/OD loop, tuning the fin shape and well dopant profile to boost the device performance. Co-work with Module to complete the key process and technology transfer to fab for production. It make me to understand what is silicon foundry and learn the process integration. In N5. Responsible for FEOL/PO loop, tuning the gate profile to boost device performance and defect reduction for yield improvement. I drive myself as a loop leader and act as a bridge between member and manger, schedule control, managing the resource by cross-departments. In these 2yrs, R&D for N2 Technology node developing, it is my first time to touch world first Gate all around(GAA) MOS process. I am being a captain for new tech developing. For schedule control, bridge the cross-team work to make suitable decision and alignment. For yield improvement, using failure analysis(EFA/PFA) and process integration experience to find out the low yield root cause. I have the ~8 years working experience in semiconductor in silicon foundry, process integration for new technology development (R&D). I believe I can handle Project/Product related tasks and co-work with cross-team work well. Try my best to make the project successfully.