Tim Vanderhoek

Background

About Tim Vanderhoek

Tim Vanderhoek has spent 20+ years in engineering, working both as an individual contributor and as an engineering manager. He has managed teams ranging in size from five engineers to over thirty-five engineers. He has a track record of developing flexible and agile teams that are able to quickly respond to changing requirements and scenarios. He takes pride in developing hybrid teams that are passionate about their projects, and believes that team structure and modus-operandi should reflect the make-up of the team. As a manager, he tends towards transparency, and delegation where possible, empowering the individuals and managers within the team to succeed. As an individual contributor, he is driven by a belief in understanding a given technical project at multiple levels of abstraction, and a desire to learn new technology related to a given project. Tim's experience includes fives years leading the team responsible for developing the Altera FPGA AI Suite (including the soft logic IP, the ML compiler, the optional host runtime, and the PCIe-attach, SoC, and hostless example designs), as well as sixteen years of background in FPGA routing and logic. Tim's list of patents, publications, and presentations speak towards a proven history of success in multiple technical areas.