Timothy Ehrler
Sr Manager Systems Engineering Pmts, Design Infrastructure Enablement, Engineering Grid IT at Amd
Based in Austin, United States
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Seniority
Manager
Department
Engineering
Location
Austin
Industry
Semiconductor Manufacturing
Company size
62K
Contact information
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t•••••••@amd.com
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Background
About Timothy Ehrler
PMI certified project manager & Senior Member with extensive engineering, management, and liaison expertise among senior management, technology partners, & industry coalitions, with proven expertise in architecture and development of semiconductor design methodologies and software applications. • Managed the relocation of EDA tool license services for primary services & disaster recovery, including infrastructure replacement and associated s/w & licensing • Managed the EDA tool licensing services management system upgrade including infrastructure replacement and associated license & daemon migration • Managed the major issue management system upgrade including all infrastructure, networking, and associated application software and database migration • Managed comprehensive evaluation of the enterprise IP, knowledge management, and defect/issue infrastructure by assessing the design process from requirements to implementation enabling informed recommendations and strategic decisions in the area of PLM/tools/services/etc • Project leadership for re-architecture and integration of existing and acquired design flows within the Sea-of-IP design environment enabling IP creation, management, distribution, interoperability, and reuse • Managed the planning, implementation, and delivery of a relative-placement tool for 45nm node semiconductor designs after assuming management of previously troubled, nonviable project efforts • Project management and co-architecture of 90nm CMOS SoC Design Environment supporting >6700 engineers world-wide and contributing to >EUR 4.6 billion in sales • Leadership role for adoption of OpenAccess design database across design environments, providing formal project management that improved interoperability and IP reuse targeting 65nm CMOS technology • Coordinated efforts between technology groups, Crolles Alliance (Philips, STMicroelectronics, and Freescale), and EDA vendors to ensure consistent OpenAccess design database interoperability
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