Timothy Stotts

Background

About Timothy Stotts

Computer engineer with over 15 relevant years of professional experience in developing and testing embedded software and programmable hardware; and also, in developing related custom Windows/Linux software tools. Particularly interested in technology designs that contribute to the well-being of society through non-consumer products.A knowledgeable engineer who frequently functions in the role of an internal technical reference, including feasibility studies.Recently conducted work experience in the areas of: Xilinx PetaLinux; modern C++; Xilinx Zynq Ultrascale MPSoC software, block design, and RTL; Xilinx APSoC; VHDL RTL and Test-bench; Verilog RTL; AXI4 RTL; microcontroller/SoC software in C/C++; drafting feasibility studies; image sensors usage, imaging algorithms, and imaging embedded system architecture.Recently conducted self-instruction in the areas of: Xilinx Spartan-7 FPGA, Xilinx Artix-7 FPGA, Xilinx APSoC, VHDL-2008 for RTL and Test-bench, Verilog-2001 for RTL, SystemVerilog (~2012) for RTL, OS-VVM with VHDL-2008, Python 3, C, C++ including design patterns and STL.Current specialties: FPGA; Vivado block design, VHDL, Verilog; Embedded C; Embedded C/C++; XML; Xilinx APSoC; ARM64 Xilinx PetaLinux with Yocto; laboratory instrumentation; robust firmware development; Agile methodology with GIT-based tools; general technical product/project development; working in a multidisciplinary environment.Past specialties: Passenger Train Cab Signaling; Embedded Microcontroller Linux; Digital Signal Processing; C#.NET; XML SOAP; SNMP; Ethernet networking; Python 3 with scientific math algorithms; top-down or bottom-up, edge-in design by documentation and modeling; UML; domestic and international travel; on-site testing with customers and co-contractors; interfacing with V&V and manufacturing departments.https://timothystotts.github.io/As recreation- Previously engaged in publishing FPGA designs on GitHub- Previously engaged in the study of SystemVerilog for RTL for FPGA logic design- Previously engaged in the study of Python 3- Previously engaged in the study of Ruby 2.6- Previously engaged in the study of C++ with STL.