Uday Doddannagari

Background

About Uday Doddannagari

CAD Principal Engineer/Manager with 17 Years of experience in RTL to GDS tools and flows.• Hands on experience in several aspects of the flow including UPF Low power Implementation for Multi-voltage designs, Synthesis, Floorplanning, Die area optimization, Place & Route and Signoff for both SoC and Block level.• CAD chip lead for the latest premium tier SoC overseeing development and support of Synthesis, scan stitch, Low power methodologies.• Experienced in driving RTL-to-GDS initiatives for optimal PPA of designs• Extensive Knowledge of EDA tools, Latest technology nodes and the challenges involved.• Experience in development and deployment of novel node-based framework for tapeout execution.• Extensive experience working with EDA vendors driving development of tool features• Strong debug skills. Strong coding skills in Tcl, Perl and PythonSKILL SET: • EDA Tools: DC-NXT, Fusion Compiler, ICC2/ICC, Genus, RTL-Architect, Innovus, Conformal low power, Conformal LEC, StarXT, Primetime, Calibre, Redhawk• Scripting skills : Python, Perl, Tcl, Shell scripting.• HDL : Verilog, VHDL, HSPICE, HSIM, SPICE3, SpectrePATENTS & PUBLICATIONS “Multi Supply Cell Array For Low Power Designs”, US PATENT No: 9483600, Issued November 1 2016 "Fast characterization of parameterized cell library", International Symposium on Quality Electronic Design (ISQED), 2009.