Utpala Jasti

Background

About Utpala Jasti

Strong background in CPU physical design engineering, with over 10 years of experience in ASIC design. Consistently achieved successful tape outs by converging multiple blocks on low design nodes and various design technologies (18A,3nm,7nm,10nm,14nm)- Collaborated with cross-functional teams for successful tape-outs on both Intel and TSMC foundries, ensuring projects were completed on time and met quality standards- Proven ability to develop, debug, and optimize SoC designs- Successful track record of executing complex multi-million gate designs through all stages, including floor-planning, placement, clock tree synthesis, routing, extraction, timing convergence, ECOs, FEV, physical verification (DRC, LVS), VCLP, reliability verification (EM IR), and noise convergence- Knowledgeable in low-power design techniques, multi-voltage designs and UPF flows- Experience enhancing design PPA (power, performance, and area) and optimizing methodologies to achieve these goals through automation, working closely with CAD and infrastructure teams- Skilled in physical design methodologies and tools such as Synopsys ICC2, Fusion Compiler, and Design Compiler- Proficient in signoff tools including Primetime, Calibre DRC/LVS, Formal Verification, and PTPX- Experienced with scripting languages like TCL, Perl and Python (basics)- Excellent team player with proven success and experience working on large technology projects for a global firm.