Vedant Gala

Background

About Vedant Gala

I thrive on challenges that push me to grow, both professionally and personally. I believe in a systems-driven approach to problem-solving — combining discipline, precision, and efficiency to deliver solutions the right way.Currently, I work in the field of pre-silicon IP functional verification, the most critical and time-intensive stage of the VLSI design flow. Verification is a way to ensure that the chip works before the chip is even fabricated!My experience spans across "functionally" verifying Memory Controllers, Arbiters, MMUs, NoC Interconnects, Coherency Fabrics, and System-level Caches, contributing at both unit-level and integration-level testbenches. Some of these testbenches were adapted to serve Chiplets and Dielet based technologies. All of these modules lie somewhere within the memory pipeline. I’ve been part of teams that built verification environments from scratch, handling everything from testbench bring-up to complex testplans around features, scenario validation and coverage closure.Key strengths- Clear, concise communication and structured thinking- Writing scalable, reusable code for robust testbenches- Deep-dive debugging to root-cause intricate functional failures- Driving documentation and productivity flows to uplift team efficiency- Advocating for clean code, strong team culture, and process optimizations.Technically, I’m proficient in VHDL, Verilog, SystemVerilog (UVM methodology), and adept at scripting with Perl and Python for automation and verification infrastructure.Lately, I’ve been extending my systems-driven approach to software — exploring full-stack development and open-source projects to bridge my hardware roots with scalable software design.