Vikrant Singh Chaudhary

Background

About Vikrant Singh Chaudhary

Hi, I'm Vikrant Singh Chaudhary, a passionate VLSI and Embedded Systems Engineer with a strong background in RTL design, verification methodologies, and FPGA-based design. I specialize in Verilog, SystemVerilog, and UVM — and I’ve spent countless hours debugging, designing, and verifying complex systems to ensure they meet performance and compliance standards. What I Bring to the Table- Expertise in Verilog, SystemVerilog, and UVM for hardware verification - Proficient in APB, AHB, AXI, SPI, and I2C protocols - Hands-on experience with leading EDA tools like ModelSim, QuestaSim, Synopsys VCS, Vivado, and ISE - Skilled in developing functional coverage models, assertions, and debugging using waveform analysis - Strong programming and scripting skills in C, C++, Python, and Shell Scripting Key Projects- DMA Controller Verification – Developed a UVM-based verification environment for AXI/APB interfaces with functional coverage and assertions- SPI Controller Verification – Verified a single master-multiple slave SPI interface using UVM methodology- APB Protocol Verification – Built a complete UVM testbench to validate APB protocol compliance through constrained-random testing- Router 1x3 Verification – Verified 8-bit data packet routing to multiple destinations using UVM- Synchronous FIFO Verification – Achieved 100% functional and code coverage for FIFO using Questa Coverage and VCS. Why Me? I’m detail-oriented, passionate about problem-solving, and thrive in fast-paced environments where innovation and precision matter. My experience in verification, coupled with a strong foundation in design and scripting, allows me to deliver high-quality, scalable solutions. I’m always open to exciting opportunities in VLSI Verification — let’s connect and explore how I can add value to your team!