Visesh Kodali
Design Verification Engineer at Astera Labs
Based in Saratoga, United States
7-day free trial · no credit card
Seniority
Staff
Department
Information Technology
Location
Saratoga
Industry
Semiconductor Manufacturing
Company size
699
Contact information
Reveal Visesh's email and phone
Direct contact data is gated. Sign up and reveal. You only pay for verified records.
v•••••••@asteralabs.com
Phone
5 credits+1 ••• •••• ••••
You only pay for valid records. Bounced emails and disconnected numbers cost nothing.
Background
About Visesh Kodali
Currently a graduate student at SJSU. Skills-SOC Design, Bus architectures, Arbitration-Digital Design using Verilog and SystemVerilog. STA, Power analysis, optimization-Verification using UVM, constraints, and randomization. Generation of reusable UVM classes and developing reference models-Computer Architecture: RISC-V and MIPS ISAs. memory hierarchy, virtual memory, cache management and architecture, coherency. Pipelining, Data hazards, Branch prediction. Out of Order execution (Tomasulow's Algorithm)
Decision-makers
Other people at Astera Labs
- SDStaff
Sam Daou
Field Application Engineer · Information Technology
- DTDirector
Damon Tohidi
Soc Design Director · Advertising & Marketing
- CMOther
Casey Morrison
Chief Product Officer, Co-founder · Other
- KVStaff
Kevin Vermilion
Distinguished Hardware Engineer · Information Technology
- SKStaff
Shafnas Km
Senior Verification Engineer · Information Technology
Build a list of verified contacts at Astera Labs
Free for 7 days · 50 credits · no card · only pay for verified records.
Reach more buyers like Visesh
250M+ professionals with verified email and phone. You only pay for records that actually verify.
7-day trial · no credit card · cancel anytime