Vivek Desai

Background

About Vivek Desai

A well experienced VLSI Physical Design Engineer offering 9+ years of rich experience focusing on the microelectronics design Industry. Specialized in working with technologies from 28 nm to 5 nm of VLSI Physical Design with designs for foundries like TSCM, GlobalFoundries and Intel. I am expertise in PnR (from synthesis to GDSII ) managing various challenges related to block Floorplan, Placement, CTS, Routing, DRC-LVS, Timing analysis etc. My recent expertise lies in subsystem / partition level floor-planning of complex compute systems and peripherals and I have about 4 years of experience handling and delivering two complex subsystems successfully. Some of my special attributes include • Subsystem floor-planning : Adept at Design Architecture understanding from subsystem floorplan point of view, Design Improvements, floor planning, Data Flow Analysis, Space Planning, pin placement for subsystem and blocks, Global Signal Routing, custom buffering and routing, Automation, Functional Blocks, Channel Blocks, Pipeline Stage, and Estimation. • Block PnR execution: Meticulously executed 5 blocks with moderate to high complexity, 3 blocks with macro count>200, 4 blocks with macro count>150, and 3 blocks with macro count > 120 and 3 blocks with IP like SERDES, ADC, PLL etc. These also include rectilinear blocks and customized CTS and buffering. • Block signoff: Worked on signoff of blocks wrt. Timing ( PT, Tempus ), DRC / LVS ( Calibre ), Power ( Redhawk ), Formality, Audit etc and delivered them successfully. • Dexterous in scripting like ECO flow automation, power rail offset checking script (top-level alignment), pin placement script for multi-fanout feedthroughs, pin alignment and placement, TCL scripting (floorplan checks automation) and attributes checking on cells/reports etc. In addition to my personal experience and qualities, I have a solid educational background in Post-graduation in Diploma in VLSI from CDAC ACTS Institution, India and Bachelor of Engineering in Electronics and Telecommunication from the University of Pune, India. In my free time I like to play music (drums) with my band, travel and do travel photography. I also have won some awards in photography competition, logo design competition, battle of bands competitions during the years in organizations. SKILLS • Physical Design ( PnR and signoff ) • Subsystem / Partition Floorplan. • Layout • Floor plan • Placement • CTS • Routing • DRC/LVS • EM /IR • Power • STA • TCL Scripting • MS Visio • Innovus • Scripting • ICC, ICC II • Calibre • Tempus