Yanto Suryono

Background

About Yanto Suryono

More than 11 years of experience in front-end digital and system designs combining wide-range skills from signal processing design and modelling, design implementation in both RTL and firmware, verification using state-of-the-art methodologies to back-end design interaction and interfacing. Specialties: Digital signal processing, RTL/firmware implementation and verification. In details- Experienced in Matlab/Simulink modelling and performance evaluation of digital signal processing data and control paths- Experienced in RTL implementation using major hardware description languages (VHDL/Verilog/SystemVerilog)- Experienced in complete front-end flow from design, RTL/Gate simulation, synthesis, lint, formal equivalency check, STA, test pattern generation- Experienced in advanced verification using UVM/SVA for constrained random stimulus generation and assertion based verification, PSL based functional formal verification- Strong hardware/software knowledge and experience enabling co-simulation and design for SoC.