Yasuo Kamiya

Background

About Yasuo Kamiya

Apr. 1987 Started working at Fujitsu, assigned to support Standard Cell ASIC development for Japanese domestic customer including frontend, backend design, customer support and factory logistics, testing for several customers. working for 'flow development'​ for Embedded Array using SOG design flow- Mar. 1996 Working for 'flow development' for Embedded Array using SiArc Layout block, flow was developped but not used in the actual design- Jul. 1997 Library support for Fujitsu ASIC implementation using Compass Standard cell library- Apr. 1998 Started working for In-House design flow (SCCAD1) development- Jul. 1998 Started working for In-House design flow (SCCAD2) development- Oct. 1998 Support actual European design using SCCAD1 design flow at Manchester, UK for one month and taped out finally- Mar. 1998 Working for Magma design flow ( very short term ). Started working for Standard cell chip layout flow implementation on IPSymphony (In-House Web-based design framework), visiting San Jose design centre two months to explain how to use to design centre members- Oct. Working for a large network ASIC chip development at San Jose for almost one year but visiting basis, introduced several new tools for chip implementation- Feb. 2002 Moved to Manchester, UK ASIC design centre and support European network ASIC designs using In-House design flow (SCCAD2)- Apr. 2003 Moved to Frankfurt, Germany ASIC design centre and support European ASIC designs, introduced new In-House design flow (Fujitsu RDF) to new designs- Jan, 2008 Back to Japan and assigned to chip implementation work for Korean ASIC customers- Apr. 2009 Moved to ASIC support team for Korea and China customers- Dec. 2012 Moved to San Jose, USA to support large chip implementation. Support and do actual chip implementation for several ASICs.