Yi Liu
Physical Design Manager at Marvell Technology
Based in China
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Seniority
Manager
Department
Engineering
Location
China
Industry
Semiconductor Manufacturing
Company size
12K
Contact information
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y•••••••@marvell.com
Phone
5 credits+86 ••• •••• ••••
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Background
About Yi Liu
Completed about 300 chips physical verification and tapeout project, included the biggest chip 17cm*17cm and about 8cm*8cm mobile chips 2. Completed 3 audio chip(100K gates) pnr projects by using ICC3. Completed 40nm/28nm storage digital and analog IP test chip PNR projects4. Managed and completed 28nm high utilization 85%chip (1.6cm*2cm < 1M gates) PNR projects5. Managed and completed 40nm chip(3cm*3cm <100K gates) PNR projects6. Managed and completed about 30 (<100K) digital block pnr projects
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