Zeeshan Rafique
Cpu Verification Engineer at Semidynamics
Based in Barcelona, Spain
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Seniority
Staff
Department
Information Technology
Location
Barcelona
Industry
Semiconductors
Company size
148
Contact information
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z•••••••@semidynamics.com
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Background
About Zeeshan Rafique
Hardware Design & Verification Engineer with 5+ years of experience in SystemVerilog, RISC-V processor design, RISC-V Vector, Floating Point 754), microarchitecture, Out of Order execution, interconnects (AXI4, TileLink-UL, Wishbone), memory-mapped I/O (UART, SPI, QSPI, PWM), System-on-Chip communication, resource-efficient hardware implementation, Advance UVM, functional coverage, random instruction generation, assembly language, and automation with Python. As a RISC-V Ambassador, I have delivered several talks to promote and encourage the adoption of RISC-V in the local community. Additionally, I have trained and mentored more than 60 undergraduate students, helping them enter the semiconductor industry. Email: zeeshanrafique23@gmail.com GitHub: zeeshanrafique23
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