David Neves

Background

About David Neves

Experience in a wide range of digital design disciplines, ranging from RTL design and verification, to physical implementation (GDSII). Have worked with a broad set of CAD/EDA tools and methodologies: Simulation, Synthesis, Place and Route, ATPG, and others. Good knowledge of several HDL and HVL languages: VHDL, Verilog, Verilog-AMS, System Verilog. Also some experience of programming and scripting languages mainly for design automation tasks: C++, Java, Python, TCL/TK, Perl, Unix shell scripts. Good command of Windows and Unix/Linux operating systems, from a user perspective as well as some knowledge from an administrator perspective. Specialties: RTL design and verification. Verification of mixed signal designs (using Verilog-AMS).