Debashree Ghosh

Background

About Debashree Ghosh

SENIOR DESIGN ENGINEER WITH EXPERIENCE OF MULTIPLE PRODUCT TAPEOUTS ON GLOBAL TEAMS AT INTEL CORP. I am a design engineer with several years of experience in CPU and server SOC design. Following a planned break from work, I am looking forward to returning to the semiconductor industry and applying my design experience and skills in creating trailblazing products. I contributed to global teams at Intel which have successfully taped out 5 microprocessors and server chips on various process nodes from 180nm to deep-submicron 14nm. Initially, I was focused on challenging custom static and domino high-speed datapath designs. As design implementation cycles have shrunk, I have gained expertise in EDA flows in designing blocks from RTL to GDSII. I have won multiple awards for the quality of my work and results orientation. These awards reflect some of the valuable skills and traits that I bring to the table. My natural inclination to plan and organize my work meticulously leads to realistic timelines, clear status updates and superior communication to the stakeholders involved. My attention to detail equips me to catch flaws hidden from others and influence project schedule arcs. My inherent desire for efficiency motivates continual feedback to improve project methodologies where broken. I am curious by nature and enjoy learning new skills which is an asset in a rapidly changing environment. I would love to have a conversation about any suitable openings on your team. Please contact me at debashreegghosh gmailcom or 408.650.7712 Skills: Synopsys synthesis, place and route (P&R), STA (DCT, ICC, Primetime), Conformal LEC verification, SPICE simulation. Floorplanning, power and clock distribution, hard IP integration IR drop analysis, Signal Integrity, OCV/AOCV analysis Low power techniques, deep-submicron challenges Programming: TCL, Shell(bash), Python