Emre Aslan

Background

About Emre Aslan

Designing and implementing PCIe endpoint device for Gen1/2/3 2. Working in the PCIe Application Layer, Transaction Layer, Data Link Layer and MAC as an architect and designer. Implementing higher-level model of Transaction Layer and Application Layer. I have experience in using PCIe IPs and setting a SoC block designs by using DDR, AXI Peripherals, Data Mover, and MicroBlaze soft core to capture data and enhance debug of PCIe EP. controller. I have guided the development of a PCIe linux driver for a 7-Series PCIe IP and developed a user test interface to sent TLPs including memory and I/O and printing PCIe configuration space header. Hands-on experience on instruction cache verification that is designed for the RISC-V processor and UVM based verification process proceeded. The necessary agents were used including sequencer, drivers, monitors, predictor and scoreboard.