Huiyan Cheah

Background

About Huiyan Cheah

I am a front-end silicon design engineer. I integrate various IPs into the FPGA. Before returning to the industry, I spent 7 years in academia studying embedded systems and computer engineering. Here is a list of useful skills I've acquired along the way:Industry• Full chip RTL integration of programmable devices• Integration tools, flows and sanity checks to ensure readiness of RTL for verification, device modelling and physical design• Infrastructure and flow setup of next generation FPGAs• Communication of requirements with stakeholders• Leading projects, training team members, sharing of knowledgeAcademia• Verilog and SystemVerilog (fluent), VHDL (basic)• FPGA development process: RTL architectural design, logic synthesis, user constraints, place-and-route, floorplanning, bitstream programming• RTL design, verification, and debugging using HDL simulators waveform editors • Testbench development, bus functional models, checkers and trackers for RTL modules• Hardware accelerators on SoC systems• HDL simulators: Modelsim, NCSim, Questasim, VCS• Automation of tasks using shell, bash, Python scripts• Xilinx ISE, EDK, Altera Quartus II, Qsys toolsets; Virtex 6 and Stratix 5 FPGAs• Hands-on experience in FPGA platform boot-up• Academic writing and presentation skillsMisc: Embedded C, C++, Compilers, parallel programming, database processing, LInux, high performance computing, embedded systems