Priya Anil Kumar

Background

About Priya Anil Kumar

Experienced Senior Engineer with 7 years of expertise spanning FPGA design and ASIC verification. Specifically, 4 years in FPGA RTL Design and verification, complemented by 3 years in ASIC design verification specializing in GLS and IP level verification with PCIe protocol.Expert in VHDL, Verilog, and Embedded C with a proven track record in RTL development and verification. Proficient with industry-standard tools including Altera Quartus Prime, Xilinx Vivado, Synopsys VCS, Verdi, and ModelSim.Extensive design verification experience including developing comprehensive test plans, creating and executing testbenches, and performing thorough simulations. Skilled in gate-level simulation, X propagation debugging, and SDF annotations for ASIC verification. Demonstrated expertise in PCIe & CXL verification and LTSSM state debugging.Specialized in protocol implementations including I2C, SPI, and UART. Demonstrated expertise in integrating complex systems.Strong debugging capabilities using SignalTap Logic Analyzer and comprehensive validation methodologies. Effective team collaborator with excellent written and oral communication skills. Consistently delivers high-quality, reliable designs while maintaining clear client communication and status reporting.​