Riccardo Sciuto

Background

About Riccardo Sciuto

Driven and enthusiastic RF/mmW Layout Engineer with 20+ years of relevant industry experience in developing ICs in advanced CMOS processes. Passionate about floor planning, top level chip assembly and high performance RF/analog blocks/IPs development with a proven ability to consistently meet deadlines ensuring the highest level of accuracy and quality on each ICs/IPs managed. Persistent in providing the best in class layout solutions by a continuous update of both technical and technological knowledge. Committed about establishing a strong collaboration with circuit designers to develop solid, robust and efficient physical designs and well-versed in leading a spread-out pool of layout engineers. Skills: • Expert on full custom RF/mmW ICs development; • Master on EDA tools: Virtuoso Layout (GXL), Mentor Calibre DRC/LVS/DRV/PEX, Design Sync; • Substantial experience on advanced CMOS (28nm, 40nm) and BiCMOS (55nm, 90nm, 0.25um, 0.35um) technologies; • Expert on detailed transistor-level layout of RF and mmW blocks (i.e. PA, VCO, Mixer, PLL, Filters, Doubler); • Strong knowledge on RF back end peculiarities (Cross-talk, High frequency routing and RF shielding, trade of parasitics and EM, RC delay, and coupling effects; • Familiar with guard rings, DNW, PN junctions, NTN, LU risks mitigation and advanced process effects such as LOD, WPE, STI; • Master with Pad ring (WB and FC), ESD, Bonding Diagrams for ICs Packaging; • Familiar with Fab reservations, Masks Request and tape out (>20 MPW, MLR, Single and Full masks set), Metal Options, Failure Analysis support; • Proficient with SKILL (CADENCE) and SVRF (MENTOR) scripting.