Eric Charlet

Background

About Eric Charlet

Plan to redirect my career in cybersecurity - Started an Msc at Cork CIT but currently on hold.=> Executive MBA (Global GPA: 3,4 - Final Grade/Average: 17/20), specialized in project management, capstone related to Industrie 4.0.=> 17 years Technical expertise in System on Chip, CPU, GPU physical design, Committed to success of projects, ability to lead and train people, proactive, perseverant, analytical mind, perfectionist * Executive MBA at Skema Business School: Project Management Specialization. Beeing an applicant to a voluntary departure plan, I attended an Executive MBA course (part time training) with the aim to develop management skills. Format: blended learning (face-to-face residential weeks, webinar courses and independent online modules) with 25 days out of the office. Locations: two weeks in France and four weeks on SKEMA’s international campuses —one week each in Raleigh, NC (USA), Suzhou (China), Belo Horizonte (Brazil), Oslo (Norway)* CPU/GPU/SoC FrontEnd & Physical Designer: Strong of more than ten years Static Timing Analysis expertise. Being used to model advanced design features from timing point of view like- Deskew PLL uncertainties due to OCV on feedback loops - Bus Synchronizers timing constraints to ensure a proper working of such synchronizers - Advanced clock gating checks. Strong knowledge of LPDDRn timings Standards & architecture. Used and trained to physical design using Cadence EDI, SoCEncounter, Synopsys IC Compiler I & II with a low power context (CPF/UPF). Physical Implementation of ARM Cortex A53 Cores. Short experience related to RTL Design of multicore ARM Cortex A53 CPU sub-System Process Monitoring Box (Used for Adapative Voltage Scaling (AVS) of Cpu sub-system). Recent experience of Synopsys Spyglass constraints for Clock Domains Crossing Checks (CDC) of Cpu subsystem.